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Webinar on "Making the Raven chip: How to design a RISC-V SoC"? - With Kunal Ghosh

Sat, 10 Mar 9:00AM - 1:00PM
Rs 940
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We really apologize for postponing this webinar 10th March. Let's pray for the families of people and instructors who were hit due to the major power outage as Nor'easter slams Massachusetts and Maryland.

Did you know there is no standard definition for GPIOs? Thats the whole point of designing an SOC. Figuring out what things you are going to control outside of the CPU and memory mapping them.

If you look at any microcontroller e.g. PIC microcontroller, the only way to know how you access their ADC or their UART is to go look at their documentation and find out wheres the memory map address for this

Do you want to know how to build and configure your own System-on-Chip (SoC)? Do you want to write your own data sheet?

I welcome you to my webinar on Mar 10. Here's the registration link:

Enroll and rise above, by being a Core SoC designer and build your own datasheet. All the best, and I will see you in webinar..

Building a chip is like building a city...
This was the mantra with which we started our company in 2011. Now that we have covered major components of chip designing through our online courses, I think this is the right time to move from "chip designing" to "chip planning"

Chip Planning involves lot of decision making like, analog peripheral (ADC, DAC, POR, etc.), digital peripheral (UART, flash controller), memory mapping, top level connections like pad-frame, level-shifters, GPIO and many more.

Do you want to know what it is like to build a city? Enroll in webinar on 10th March from 9am to 1pm IST with myself, Tim Edwards and Mohamed Kassem. Details of registration link will be published soon.

This is the perfect webinar for to grow and stay ahead of curve in Semiconductor and Chip design. Stay tuned and happy learning....

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Webinar Description

Webinar Description
  1. .Raven SoC overview
  2. Run-through of Raven files:
         (A) picorv32
         (B) raven_spi
         (C) raven_soc
         (D) digital peripheral (UART, flash controller)
         (E) memory (SRAM)
         (F) analog peripheral (ADC, DAC, POR, etc.)
         (G) padframe
  3. Further description of SoC and choice of
         connections between blocks
  4. Memory map description
  5. Top-level connections: padframe, level shifters, multiplexers
  6. Testbench C code
  7. Testbench verilog code
  8. Makefile run-through
  9. Running testbench series (GPIO, ADC, DAC, UART)
  10. Example:  Create a new testbench to test bandgap voltage and use bandgap as reference to test the comparator.
  11. Example:  Run the new testbench and verify operation.
  12. Overview of synthesis process
  13. Challenge:  Add a general-purpose timer/counter module to raven_soc
            (A) driven from selectable sources:
                    (i)   master clock
                    (ii)  crystal clock
                    (iii) external clock
                    (iv)  RC oscillator output
            (B) 32 bits
            (C) Timer output routed to GPIO or interrupt
            (D) Counter output memory mapped
            (E) Control values are the amount to add to the counter per
                clock cycle and the value at which to toggle the timer output.
            (F) One-shot or continuous
            (G) Continuous mode may restart at zero or wrap around

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